DAC module and applications thereof

ABSTRACT

A digital to analog conversion (DAC) module includes a digital to analog converter, a sample and hold circuit, and a switch module. The digital to analog converter is coupled to convert a digital signal into an analog signal. The sample and hold circuit is coupled to sample the analog signal to produce a sampled analog signal. The switch module is coupled to provide the analog signal as an output of the DAC module when the DAC module in a first mode and to output the analog signal to the sample and hold circuit when the DAC module in a second mode, wherein the sampled analog signal provides the output of the DAC module in the second mode.

CROSS REFERENCE TO RELATED PATENTS

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INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC

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BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

This invention relates generally to wireless communication systems andmore particularly to components of transmitters used within suchsystems.

2. Description of Related Art

Communication systems are known to support wireless and wire linedcommunications between wireless and/or wire lined communication devices.Such communication systems range from national and/or internationalcellular telephone systems to the Internet to point-to-point in-homewireless networks. Each type of communication system is constructed, andhence operates, in accordance with one or more communication standards.For instance, wireless communication systems may operate in accordancewith one or more standards including, but not limited to, IEEE 802.11,Bluetooth, advanced mobile phone services (AMPS), digital AMPS, globalsystem for mobile communications (GSM), code division multiple access(CDMA), local multi-point distribution systems (LMDS),multi-channel-multi-point distribution systems (MMDS), radio frequencyidentification (RFID), Enhanced Data rates for GSM Evolution (EDGE),General Packet Radio Service (GPRS), and/or variations thereof.

Depending on the type of wireless communication system, a wirelesscommunication device, such as a cellular telephone, two-way radio,personal digital assistant (PDA), personal computer (PC), laptopcomputer, home entertainment equipment, RFID reader, RFID tag, et ceteracommunicates directly or indirectly with other wireless communicationdevices. For direct communications (also known as point-to-pointcommunications), the participating wireless communication devices tunetheir receivers and transmitters to the same channel or channels (e.g.,one of the plurality of radio frequency (RF) carriers of the wirelesscommunication system or a particular RF frequency for some systems) andcommunicate over that channel(s). For indirect wireless communications,each wireless communication device communicates directly with anassociated base station (e.g., for cellular services) and/or anassociated access point (e.g., for an in-home or in-building wirelessnetwork) via an assigned channel. To complete a communication connectionbetween the wireless communication devices, the associated base stationsand/or associated access points communicate with each other directly,via a system controller, via the public switch telephone network, viathe Internet, and/or via some other wide area network.

For each wireless communication device to participate in wirelesscommunications, it includes a built-in radio transceiver (i.e., receiverand transmitter) or is coupled to an associated radio transceiver (e.g.,a station for in-home and/or in-building wireless communicationnetworks, RF modem, etc.). As is known, the receiver is coupled to anantenna and includes a low noise amplifier, one or more intermediatefrequency stages, a filtering stage, and a data recovery stage. The lownoise amplifier receives inbound RF signals via the antenna andamplifies then. The one or more intermediate frequency stages mix theamplified RF signals with one or more local oscillations to convert theamplified RF signal into baseband signals or intermediate frequency (IF)signals. The filtering stage filters the baseband signals or the IFsignals to attenuate unwanted out of band signals to produce filteredsignals. The data recovery stage recovers raw data from the filteredsignals in accordance with the particular wireless communicationstandard.

As is also known, the transmitter includes a data modulation stage, oneor more intermediate frequency stages, and a power amplifier. The datamodulation stage converts raw data into baseband signals in accordancewith a particular wireless communication standard. The one or moreintermediate frequency stages mix the baseband signals with one or morelocal oscillations to produce RF signals. The power amplifier amplifiesthe RF signals prior to transmission via an antenna.

While transmitters generally include a data modulation stage, one ormore IF stages, and a power amplifier, the particular implementation ofthese elements is dependent upon the data modulation scheme of thestandard being supported by the transceiver. For example, if thebaseband modulation scheme is Gaussian Minimum Shift Keying (GMSK), thedata modulation stage functions to convert digital words into quadraturemodulation symbols, which have a constant amplitude and varying phases.The IF stage includes a phase locked loop (PLL) that generates anoscillation at a desired RF frequency, which is modulated based on thevarying phases produced by the data modulation stage. The phasemodulated RF signal is then amplified by the power amplifier inaccordance with a transmit power level setting to produce a phasemodulated RF signal.

As another example, if the data modulation scheme is 8-PSK (phase shiftkeying), the data modulation stage functions to convert digital wordsinto symbols having varying amplitudes and varying phases. The IF stageincludes a phase locked loop (PLL) that generates an oscillation at adesired RF frequency, which is modulated based on the varying phasesproduced by the data modulation stage. The phase modulated RF signal isthen amplified by the power amplifier in accordance with the varyingamplitudes to produce a phase and amplitude modulated RF signal.

As the trend for wireless communication devices to support multiplestandards continues, recent trends include the desire to integrate theRF portions (i.e., the one or more IF stages and the power amplifier) ofGSM and EDGE on to a single chip. As is known, GSM uses a GMSK datamodulation scheme and EDGE uses an 8-PSK data modulation scheme, whichhave different requirements for the RF portion of the transmitter asdescribed above.

Therefore, a need exists for a transmitter that includes a front-endthat enables the transmitter to support multiple standards havingdifferent data modulation schemes.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to apparatus and methods of operationthat are further described in the following Brief Description of theDrawings, the Detailed Description of the Invention, and the claims.Other features and advantages of the present invention will becomeapparent from the following detailed description of the invention madewith reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

FIG. 1 is a schematic block diagram of a wireless communication systemin accordance with the present invention;

FIG. 2 is a schematic block diagram of an embodiment of a wirelesscommunication device in accordance with the present invention;

FIG. 3 is a schematic block diagram of an embodiment of an up-conversionmodule in accordance with the present invention;

FIG. 4 is a schematic block diagram of an embodiment of a DAC module andan embodiment of a power amplifier module in accordance with the presentinvention;

FIG. 5 is a schematic block diagram of another embodiment of a wirelesscommunication device in accordance with the present invention;

FIG. 6 is a schematic block diagram of another embodiment of a DACmodule in accordance with the present invention;

FIG. 7 is a schematic block diagram of an embodiment of a digital toanalog converter in accordance with the present invention; and

FIG. 8 is a schematic block diagram of an embodiment of a current tovoltage module in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram illustrating a communication system10 that includes a plurality of base stations and/or access points 12,16, a plurality of wireless communication devices 18-32 and a networkhardware component 34. Note that the network hardware 34, which may be arouter, switch, bridge, modem, system controller, et cetera provides awide area network connection 42 for the communication system 10. Furthernote that the wireless communication devices 18-32 may be laptop hostcomputers 18 and 26, personal digital assistant hosts 20 and 30,personal computer hosts 24 and 32 and/or cellular telephone hosts 22 and28. The details of the wireless communication devices will be describedin greater detail with reference to FIGS. 2-8.

Wireless communication devices 22, 23, and 24 are located within anindependent basic service set (IBSS) area and communicate directly(i.e., point to point). In this configuration, these devices 22, 23, and24 may only communicate with each other. To communicate with otherwireless communication devices within the system 10 or to communicateoutside of the system 10, the devices 22, 23, and/or 24 need toaffiliate with one of the base stations or access points 12 or 16.

The base stations or access points 12, 16 are located within basicservice set (BSS) areas 11 and 13, respectively, and are operablycoupled to the network hardware 34 via local area network connections36, 38. Such a connection provides the base station or access point 1216 with connectivity to other devices within the system 10 and providesconnectivity to other networks via the WAN connection 42. To communicatewith the wireless communication devices within its BSS 11 or 13, each ofthe base stations or access points 12-16 has an associated antenna orantenna array. For instance, base station or access point 12 wirelesslycommunicates with wireless communication devices 18 and 20 while basestation or access point 16 wirelessly communicates with wirelesscommunication devices 26-32. Typically, the wireless communicationdevices register with a particular base station or access point 12, 16to receive services from the communication system 10.

Typically, base stations are used for cellular voice and/or datatelephone systems and like-type systems, while access points are usedfor in-home or in-building wireless networks (e.g., IEEE 802.11 andversions thereof, Bluetooth, RFID, and/or any other type of radiofrequency based network protocol). Regardless of the particular type ofcommunication system, each wireless communication device includes abuilt-in radio and/or is coupled to a radio. Note that one or more ofthe wireless communication devices may include an RFID reader and/or anRFID tag.

FIG. 2 is a schematic block diagram of an embodiment of a wirelesscommunication device 18-32 that includes a host device 50 and atransceiver 52. The host device 50 may include laptop computercircuitry, personal computer circuitry, PDA circuitry, cellular voiceand/or data processing circuitry, personal entertainment circuitry,and/or a processing module. The processing module may be a singleprocessing device or a plurality of processing devices. Such aprocessing device may be a microprocessor, micro-controller, digitalsignal processor, microcomputer, central processing unit, fieldprogrammable gate array, programmable logic device, state machine, logiccircuitry, analog circuitry, digital circuitry, and/or any device thatmanipulates signals (analog and/or digital) based on hard coding of thecircuitry and/or operational instructions. The processing module mayinclude an associated memory and/or memory element, which may be asingle memory device, a plurality of memory devices, and/or embeddedcircuitry of the processing module. Such a memory device may be aread-only memory, random access memory, volatile memory, non-volatilememory, static memory, dynamic memory, flash memory, cache memory,and/or any device that stores digital information.

The transceiver 52 includes a receiver 54, a transmitter 56, and a hostinterface 58. The transmitter 56 includes a 1^(st) baseband processingmodule 60, a 2^(nd) baseband processing module 62, an up-conversionmodule 64, and a radio frequency (RF) front-end 66. The RF front-end 66includes a digital to analog conversion (DAC) module 70 and a poweramplifier (PA) module 72. The 1^(st) and 2^(nd) baseband processingmodules 60 and 62 may be separate processing modules or a commonprocessing module. Such a processing module may be a single processingdevice or a plurality of processing devices. Such a processing devicemay be a microprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module may have an associatedmemory and/or memory element, which may be a single memory device, aplurality of memory devices, and/or embedded circuitry of the processingmodule. Such a memory device may be a read-only memory, random accessmemory, volatile memory, non-volatile memory, static memory, dynamicmemory, flash memory, cache memory, and/or any device that storesdigital information. Note that when the processing module implements oneor more of its functions via a state machine, analog circuitry, digitalcircuitry, and/or logic circuitry, the memory and/or memory elementstoring the corresponding operational instructions may be embeddedwithin, or external to, the circuitry comprising the state machine,analog circuitry, digital circuitry, and/or logic circuitry. Furthernote that, the memory element stores, and the processing moduleexecutes, hard coded and/or operational instructions corresponding to atleast some of the steps and/or functions illustrated in FIGS. 2-8.

The receiver 54, which function in accordance with one or more standards(e.g., GSM, EDGE, CDMA, GPRS, etc.), receives inbound RF signals 102 andconverts them into inbound data 104. The inbound data 104 is provided tothe host device 50 via the host interface 58. For example, if theinbound RF signals are in accordance with Gaussian Minimum Shift Keying(GMSK) of a version of the GSM standard, they are phase modulated RFsignals. In this example, the receiver 64 extracts the phase informationfrom the phase modulated RF signals and converts the phase informationinto the inbound data 104. As another example, if the inbound RF signalsare in accordance with 8-PSK (phase shift keying) of a version of theEDGE standard, they are phase and amplitude modulated RF signals. Inthis example, the receiver 64 extracts phase information and modulationinformation from the phase and amplitude modulated RF signals andconverts the phase information and amplitude information into theinbound data 104.

The transmitter 56 receives 1^(st) or 2^(nd) outbound data 74 or 82 fromthe host device 50 via the host interface 58. The 1^(st) outbound data74 corresponds to data that is to be transmitted in accordance with awireless communication standard that employs a data modulation schemehaving varying amplitudes and varying phases (e.g., 8-PSK of EDGE,quadrature amplitude modulation of IEEE 802.11, etc.) and the 2^(nd)outbound data 82 corresponds to data that is be transmitted inaccordance with a wireless communication standard that employs a datamodulation scheme having varying phases (e.g., GSMK of GSM and GPRS,quadrature-PSK of CDMA, etc.).

When the host device 50 desires to transmit the 1^(st) outbound data 74(e.g., an EDGE data transmission), the host device 50 places thetransmitter 56 in a first mode. In the first mode, the 1^(st) basebandprocessing module 60 is active to receive the 1^(st) outbound data 74.The 1^(st) baseband processing module 60 converts the 1^(st) outbounddata 74 into first symbols 76 that include first phase information 76and amplitude information 80. In one embodiment, the 1^(st) basebandprocessing module 60 may encode, puncture, map, interleave, and/ordomain convert the 1^(st) outbound data 74 into polar coordinate symbolsof amplitude information 80 (A) and phase information 78 (Φ). Forexample, if the baseband processing utilizes an 8-PSK data modulationscheme, a first outbound data value and a second outbound data value maybe ½ rate encoded to produce 1^(st) and 2^(nd) encoded values. Afterpuncturing, the encoded values may be interleaved to produce a firstinterleaved value and a second interleaved value. The first interleavedvalue is mapped into an amplitude value of A₀ and a phase value of Φ₀and the second interleaved value is mapped into an amplitude value of A₁and a phase value of Φ₁.

The up-conversion module 64, which will be described in greater detailwith reference to FIG. 3, receives the 1^(st) phase information 78 andproduces therefrom 1^(st) phase modulated RF signals 90. The DAC module70 receives the amplitude information 80 and converts it into analogamplitude adjust signals 94. The PA module 72 amplifies the 1^(st) phasemodulate RF signals 90 in accordance with the analog amplitude adjustsignals 94 to produce 1^(st) outbound RF signals 98. Note that the RFfront-end 66 and/or the up-conversion module 64 may includesynchronization circuitry to insure that the 1^(st) phase modulated RFsignals 90 and the analog amplitude adjust signals 94 correspond, intime, with the 1^(st) phase information 78 and amplitude information 80.

When the host device 50 desires to transmit the 2^(nd) outbound data 82(e.g., a GSM voice transmission), the host device 50 places thetransmitter 56 in a second mode. In the second mode, the 2^(nd) basebandprocessing module 62 is active to convert the 2^(nd) outbound data 82into 2^(nd) symbols 84 that include 2 phase information 86 and may alsogenerate power level information 88. In one embodiment, the 2^(nd)baseband processing module 62 may encode, puncture, map, interleave,and/or domain convert the 2^(nd) outbound data 82 into polar coordinatesymbols of fixed amplitude (A) and 2^(nd) phase information 86 (Φ). Forexample, if the baseband processing utilizes an QPSK data modulationscheme, a first outbound data value and a second outbound data value maybe ½ rate encoded to produce 1^(st) and 2^(nd) encoded values. Afterpuncturing, the encoded values may be interleaved to produce a firstinterleaved value and a second interleaved value. The first interleavedvalue is mapped into a fixed amplitude value of A and a phase value ofΦ₀ and the second interleaved value is mapped into the amplitude valueof A and a phase value of Φ₁. The baseband processing module 62 may thengenerate a power transmission level 88.

The up-conversion module 64 converts the 2^(nd) phase information 86 ofthe 2^(nd) symbols 84 into 2 phase modulated RF signals 92. The DACmodule 70 converts the power level information 88 into analog powerlevel signals 96. The PA module 72 amplifies the 2^(nd) phase modulatedRF signals 92 in accordance with the analog power level signals 96 toproduce 2^(nd) outbound RF signals 100.

In one embodiment, the 1^(st) baseband processing module 60, the 2^(nd)baseband processing module 62, the up-conversion module 64, the digitalto analog conversion module 70, and a power amplifier driver of thepower amplifier module 70 are on a die of an integrated circuit and apower amplifier coupled to the power amplifier module 72 is an externalcomponent with respect to the integrated circuit. In another embodiment,the power amplifier module 72 includes power amplifier driver and apower amplifier that are on the same die of an integrated circuit as the1^(st) baseband processing module 60, the 2^(nd) baseband processingmodule 62, the up-conversion module 64, and the digital to analogconversion module 70.

FIG. 3 is a schematic block diagram of an embodiment of an up-conversionmodule 64 that includes a multiplexer 110 and a phase locked loop (PLL)112. The PLL 112 includes a forward path 114 and a feedback path 116.When the transmitter is in the first mode, the multiplexer 110 providesthe 1^(st) phase information 78 to the feedback path 116 of the PLL 112.The feedback path 116 (which may include a fixed divider module, afractional-N divider module, and/or a variable divider module) generatesa feedback oscillation 120 based on the 1^(st) phase modulated RFsignals 90, a divider value, and the 1^(st) phase information 78. Theforward path 114, which may include a phase and/or frequency detector, acharge pump, a loop filter, and a voltage controlled oscillator,generates the 1^(st) phase modulated RF signals 90 from a referenceoscillation 118 and the feedback oscillation 120.

When the transmitter is in the second mode, the multiplexer 10 providesthe 2^(nd) phase information 86 to the feedback path 116 of the PLL 112.The feedback path 116 generates the feedback oscillation 120 based onthe 2^(nd) phase modulated RF signals 92, a divider value, and the2^(nd) phase information 86. The forward path 114 generates the 2^(nd)phase modulated RF signals 92 from a reference oscillation 118 and thefeedback oscillation 120.

FIG. 4 is a schematic block diagram of an embodiment of a DAC module 70and an embodiment of a power amplifier module 72. The DAC module 70includes a multiplexer 130 and a digital to analog converter (DAC) 132.The PA module 72 includes a power amplifier driver 134, a poweramplifier 136, and a demultiplexer 138.

The multiplexer 130, which may be a multiplexer, switching network,and/or gating device, outputs the amplitude information 80 when thetransmitter 56 is in the first mode and outputs the power levelinformation 88 when the transmitter 56 is in the second mode. Thedigital to analog converter 132, which may be a sigma delta DAC,converts the amplitude information 80 into the analog amplitude adjustsignals 94 and to convert the power level information 88 into the analogpower level signals 96.

The power amplifier driver 134, which may include one or more driverscoupled in parallel and/or in series, is coupled in series with thepower amplifier 136, which may include one or more amplifiers coupled inparallel and/or in series. In one embodiment, the power amplifier 136 isoff-chip with respect to the power amplifier drive 134 and in anotherembodiment the power amplifier 136 is on the same chip as the poweramplifier driver 134. When the transmitter 56 is in the first mode, thedemultiplexer 138, which may be a demultiplexer, a switching network,and/or gating device, provides the analog amplitude adjust signals 94 tothe power amplifier driver 134.

In the first mode, the power amplifier driver 134 amplifies the 1^(st)phase modulated RF signals 90 in accordance with the analog amplitudeadjust signals 94 to produce driver amplified first phase modulated RFsignals. The power amplifier 136 amplifies the driver amplified firstphase modulated RF signals in accordance with a power amplifier gainsetting, which may be a default setting or programmed by the 1^(st)baseband processing module 60, to produce the first outbound RF signals98.

When the transmitter 56 is in the second mode, the demultiplexer 138provides the analog power level signals 96 to the power amplifier 136.The power amplifier driver 134 amplifies the second phase modulated RFsignals 92 in accordance with a driver gain setting, which may be adefault setting or programmed by the 2^(nd) baseband processing module62, to produce driver amplified second phase modulated RF signals. Thepower amplifier 136 amplifies the driver amplified second phasemodulated RF signals in accordance with the analog power level signals96 to produce the 2^(nd) outbound RF signals 100.

FIG. 5 is a schematic block diagram of another embodiment of a wirelesscommunication device 18-32 that includes a host device 50 and atransceiver 52. The host device 50 may include laptop computercircuitry, personal computer circuitry, PDA circuitry, cellular voiceand/or data processing circuitry, personal entertainment circuitry,and/or a processing module.

The transceiver 52 includes a receiver 54, a transmitter 56, and a hostinterface 58. The transmitter 56 includes a baseband processing module140, an up-conversion module 64, and a radio frequency (RF) front-end66. The RF front-end 66 includes a digital to analog conversion (DAC)module 70 and a power amplifier (PA) module 72. The baseband processingmodules 140 may be a processing module. Such a processing module may bea single processing device or a plurality of processing devices. Such aprocessing device may be a microprocessor, micro-controller, digitalsignal processor, microcomputer, central processing unit, fieldprogrammable gate array, programmable logic device, state machine, logiccircuitry, analog circuitry, digital circuitry, and/or any device thatmanipulates signals (analog and/or digital) based on hard coding of thecircuitry and/or operational instructions. The processing module mayhave an associated memory and/or memory element, which may be a singlememory device, a plurality of memory devices, and/or embedded circuitryof the processing module. Such a memory device may be a read-onlymemory, random access memory, volatile memory, non-volatile memory,static memory, dynamic memory, flash memory, cache memory, and/or anydevice that stores digital information. Note that when the processingmodule implements one or more of its functions via a state machine,analog circuitry, digital circuitry, and/or logic circuitry, the memoryand/or memory element storing the corresponding operational instructionsmay be embedded within, or external to, the circuitry comprising thestate machine, analog circuitry, digital circuitry, and/or logiccircuitry. Further note that, the memory element stores, and theprocessing module executes, hard coded and/or operational instructionscorresponding to at least some of the steps and/or functions illustratedin FIGS. 2-8.

The receiver 54, which function in accordance with one or more standards(e.g., GSM, EDGE, CDMA, GPRS, etc.), receives inbound RF signals 102 andconverts them into inbound data 104. The inbound data 104 is provided tothe host device 50 via the host interface 58. For example, if theinbound RF signals are in accordance with Gaussian Minimum Shift Keying(GMSK) of a version of the GSM standard, they are phase modulated RFsignals. In this example, the receiver 64 extracts the phase informationfrom the phase modulated RF signals and converts the phase informationinto the inbound data 104. As another example, if the inbound RF signalsare in accordance with 8-PSK (phase shift keying) of a version of theEDGE standard, they are phase and amplitude modulated RF signals. Inthis example, the receiver 64 extracts phase information and modulationinformation from the phase and amplitude modulated RF signals andconverts the phase information and amplitude information into theinbound data 104.

The transmitter 56 receives outbound data signals 142 or outbound voicesignals 144 from the host device 50 via the host interface 58. Theoutbound data signals 142 correspond to data that is to be transmittedin accordance with a wireless communication standard that employs a datamodulation scheme having varying amplitudes and varying phases (e.g.,8-PSK of EDGE, quadrature amplitude modulation of IEEE 802.11, etc.) andthe voice outbound signals 144 correspond to digitized voice signalsthat are be transmitted in accordance with a wireless communicationstandard that employs a data modulation scheme having varying phases(e.g., GSMK of GSM, quadrature-PSK of CDMA, etc.).

When the host device 50 desires to transmit the outbound data signals142 (e.g., an EDGE data transmission), the host device 50 places thetransmitter 56 in a first mode. In the first mode, the basebandprocessing module 140 receives converts the outbound data signals 142into data symbols 146 that include first phase information 76 andamplitude information 80. In one embodiment, the baseband processingmodule 140 may encode, puncture, map, interleave, and/or domain convertthe outbound data signals 142 into polar coordinate symbols of amplitudeinformation 80 (A) and phase information 78 (Φ). For example, if thebaseband processing utilizes an 8-PSK data modulation scheme, a firstoutbound data value and a second outbound data value may be ½ rateencoded to produce 1^(st) and 2^(nd) encoded values. After puncturing,the encoded values may be interleaved to produce a first interleavedvalue and a second interleaved value. The first interleaved value ismapped into an amplitude value of A₀ and a phase value of Φ₀ and thesecond interleaved value is mapped into an amplitude value of A₁ and aphase value of Φ₁.

The up-conversion module 64 receives the 1^(st) phase information 78 andproduces therefrom 1^(st) phase modulated RF signals 90. The DAC module70 receives the amplitude information 80 and converts it into analogamplitude adjust signals 94. The PA module 72 amplifies the 1^(st) phasemodulate RF signals 90 in accordance with the analog amplitude adjustsignals 94 to produce outbound RF data signals 150. Note that the RFfront-end 66 and/or the up-conversion module 64 may includesynchronization circuitry to insure that the 1^(st) phase modulated RFsignals 90 and the analog amplitude adjust signals 94 correspond, intime, with the 1^(st) phase information 78 and amplitude information 80.

When the host device 50 desires to transmit the outbound voice signals144 (e.g., a GSM voice transmission), the host device 50 places thetransmitter 56 in a second mode. In the second mode, the basebandprocessing module 140 converts the outbound data voice signals 144 intovoice symbols 148 that include 2^(nd) phase information 86 and may alsogenerate power level information 88. In one embodiment, the basebandprocessing module 140 may encode, puncture, map, interleave, and/ordomain convert the outbound voice signals 144 into polar coordinatesymbols of fixed amplitude (A) and 2^(nd) phase information 86 (Φ). Forexample, if the baseband processing utilizes a QPSK data modulationscheme, a first outbound data value and a second outbound data value maybe ½ rate encoded to produce 1^(st) and 2^(nd) encoded values. Afterpuncturing, the encoded values may be interleaved to produce a firstinterleaved value and a second interleaved value. The first interleavedvalue is mapped into a fixed amplitude value of A and a phase value ofΦ₀ and the second interleaved value is mapped into the amplitude valueof A and a phase value of Φ₁. The baseband processing module 140 maythen generate a power transmission level 88.

The up-conversion module 64 converts the 2^(nd) phase information 86 ofthe 2^(nd) symbols 84 into 2^(nd) phase modulated RF signals 92. The DACmodule 70 converts the power level information 88 into analog powerlevel signals 96. The PA module 72 amplifies the 2^(nd) phase modulatedRF signals 92 in accordance with the analog power level signals 96 toproduce 2^(nd) outbound RF signals 100.

In one embodiment, the baseband processing module 140, the up-conversionmodule 64, the digital to analog conversion module 70, and a poweramplifier driver of the power amplifier module 70 are on a die of anintegrated circuit and a power amplifier coupled to the power amplifiermodule 72 is an external component with respect to the integratedcircuit. In another embodiment, the power amplifier module 72 includespower amplifier driver and a power amplifier that are on the same die ofan integrated circuit as the baseband processing module 140, theup-conversion module 64, and the digital to analog conversion module 70.

FIG. 6 is a schematic block diagram of another embodiment of a DACmodule 70 that includes a digital to analog converter 150, a switchmodule 154, and a sample-&-hold circuit 152. The digital to analogconverter 150 (an embodiment of which will be described in greaterdetail with reference to FIG. 7) receives a digital signal 156 from amultiplexer 166. In one embodiment, the multiplexer 166 provides theamplitude information 80 as the digital signal 156 when the transmitteris in the first mode and provides the power level information 88 whenthe transmitter is in the second mode.

The digital to analog converter 150 converts the digital signals 156into an analog signal 158. When the transmitter is in the first mode,the analog signal 158 may be the analog amplitude adjust signals 94 andwhen the transmitter is in the second mode, the analog signal 158 may bethe analog power level signals 96. When the transmitter is in the secondmode 162, the switching module 154 (which may be a multiplexer,switching network, and/or a gating device) provides the analog signal158 (e.g., the analog power level signals 96) as the output of the DACmodule 70.

When the transmitter is in the first mode 162, the switching module 154provides the analog signal 158 (e.g., the analog amplitude adjustsignals 94) to the sample-&-hold circuit 152. The output of thesample-&-hold circuit 152 provides the output of the DAC module 70. Notethat the sample-&-hold circuit 152 is clocked such that the analogamplitude adjust signals 94 are provided to the PA module 72 insynchronization with the 1^(st) phase modulated RF signals 90.

FIG. 7 is a schematic block diagram of an embodiment of a digital toanalog converter 150 that includes a sigma delta modulator 170, acurrent amplifier section 172, and a current to voltage module 174. Thesigma-delta modulator 170, which may be a second order or greater sigmadelta modulator, converts to the digital signal 156 into a sigma-deltamodulated signal 176. The current amplifier section 172, which mayinclude a transconductance amplifier, weighted current sources, and aresistive network, converts the sigma-delta modulated signal 176 into ananalog current 178. The current to voltage module 174 converts theanalog current 178 into the analog signal 158.

FIG. 8 is a schematic block diagram of an embodiment of a current tovoltage module 174 that includes a variable current source 182 and animpedance 180. The variable current source 182 is varied based on theanalog current 178 to produce a reference current, which flows throughimpedance 180 to establish a voltage representation of the analog signal158. In one embodiment, the impedance includes a variable impedancecoupled to produce the analog signal in accordance with acurrent-to-voltage gain setting (e.g., an impedance setting set by thebaseband processing module 140). In another embodiment, the variablecurrent source 182 is coupled to produce a reference current based onthe analog current and a current-to-voltage gain setting (e.g., a biaslevel set by the baseband processing module 140).

As may be used herein, the terms “substantially” and “approximately”provides an industry-accepted tolerance for its corresponding termand/or relativity between items. Such an industry-accepted toleranceranges from less than one percent to fifty percent and corresponds to,but is not limited to, component values, integrated circuit processvariations, temperature variations, rise and fall times, and/or thermalnoise. Such relativity between items ranges from a difference of a fewpercent to magnitude differences. As may also be used herein, theterm(s) “coupled to” and/or “coupling” and/or includes direct couplingbetween items and/or indirect coupling between items via an interveningitem (e.g., an item includes, but is not limited to, a component, anelement, a circuit, and/or a module) where, for indirect coupling, theintervening item does not modify the information of a signal but mayadjust its current level, voltage level, and/or power level. As mayfurther be used herein, inferred coupling (i.e., where one element iscoupled to another element by inference) includes direct and indirectcoupling between two items in the same manner as “coupled to”. As mayeven further be used herein, the term “operable to” indicates that anitem includes one or more of power connections, input(s), output(s),etc., to perform one or more its corresponding functions and may furtherinclude inferred coupling to one or more other items. As may stillfurther be used herein, the term “associated with”, includes directand/or indirect coupling of separate items and/or one item beingembedded within another item. As may be used herein, the term “comparesfavorably”, indicates that a comparison between two or more items,signals, etc., provides a desired relationship. For example, when thedesired relationship is that signal 1 has a greater magnitude thansignal 2, a favorable comparison may be achieved when the magnitude ofsignal 1 is greater than that of signal 2 or when the magnitude ofsignal 2 is less than that of signal 1.

The present invention has also been described above with the aid ofmethod steps illustrating the performance of specified functions andrelationships thereof. The boundaries and sequence of these functionalbuilding blocks and method steps have been arbitrarily defined hereinfor convenience of description. Alternate boundaries and sequences canbe defined so long as the specified functions and relationships areappropriately performed. Any such alternate boundaries or sequences arethus within the scope and spirit of the claimed invention.

The present invention has been described above with the aid offunctional building blocks illustrating the performance of certainsignificant functions. The boundaries of these functional buildingblocks have been arbitrarily defined for convenience of description.Alternate boundaries could be defined as long as the certain significantfunctions are appropriately performed. Similarly, flow diagram blocksmay also have been arbitrarily defined herein to illustrate certainsignificant functionality. To the extent used, the flow diagram blockboundaries and sequence could have been defined otherwise and stillperform the certain significant functionality. Such alternatedefinitions of both functional building blocks and flow diagram blocksand sequences are thus within the scope and spirit of the claimedinvention. One of average skill in the art will also recognize that thefunctional building blocks, and other illustrative blocks, modules andcomponents herein, can be implemented as illustrated or by discretecomponents, application specific integrated circuits, processorsexecuting appropriate software and the like or any combination thereof.

1. A digital to analog conversion (DAC) module comprises: a digital toanalog converter coupled to convert a digital signal into an analogsignal; a sample and hold circuit coupled to sample the analog signal toproduce a sampled analog signal; and a switch module coupled to providethe analog signal as an output of the DAC module when the DAC module ina first mode and to output the analog signal to the sample and holdcircuit when the DAC module in a second mode, wherein the sampled analogsignal provides the output of the DAC module in the second mode.
 2. TheDAC module of claim 1, wherein the digital to analog convertercomprises: a sigma-delta modulator coupled to convert to the digitalsignal into a sigma-delta modulated signal; a current amplifier sectioncoupled to convert the sigma-delta modulated signal into an analogcurrent; and a voltage to current module coupled to convert the analogcurrent into the analog signal.
 3. The DAC module of claim 2, whereinthe voltage to current module comprises: a variable current sourcecoupled to produce a reference current based on the analog current; andan impedance coupled to produce the analog signal based on the referencecurrent.
 4. The DAC module of claim 3, wherein the impedance comprises:a variable impedance coupled to produce the analog signal in accordancewith a current-to-voltage gain setting.
 5. The DAC module of claim 3,wherein the voltage to current module comprises: the variable currentsource coupled to produce a reference current based on the analogcurrent and a current-to-voltage gain setting.
 6. The DAC module ofclaim 1 further comprises: a multiplexer coupled to provide a firstdigital signal as the digital signal when the DAC module is in the firstmode and coupled to provide a second digital signal as the digitalsignal when the DAC module is in the second mode.
 7. A digital to analogconversion (DAC) module comprises: a digital to analog converter coupledto convert a digital signal into an analog signal; a multiplexer coupledto provide an amplitude modulation information digital signal to thedigital to analog converter as the digital signal when the DAC module isin a first mode and coupled to provide a power level digital signal tothe digital to analog converter as the digital signal when the DACmodule is in the second mode; a sample and hold circuit coupled tosample the analog signal to produce a sampled analog signal; and aswitch module coupled to provide the analog signal as an output of theDAC module when the DAC module in the first mode and to output theanalog signal to the sample and hold circuit when the DAC module in thesecond mode, wherein the sampled analog signal provides the output ofthe DAC module in the second mode.
 8. The DAC module of claim 7, whereinthe digital to analog converter comprises: a sigma-delta modulatorcoupled to convert to the digital signal into a sigma-delta modulatedsignal; a current amplifier section coupled to convert the sigma-deltamodulated signal into an analog current; and a voltage to current modulecoupled to convert the analog current into the analog signal.
 9. The DACmodule of claim 8, wherein the voltage to current module comprises: avariable current source coupled to produce a reference current based onthe analog current; and an impedance coupled to produce the analogsignal based on the reference current.
 10. The DAC module of claim 8,wherein the impedance comprises: a variable impedance coupled to producethe analog signal in accordance with a current-to-voltage gain setting.11. The DAC module of claim 8, wherein the voltage to current modulecomprises: the variable current source coupled to produce a referencecurrent based on the analog current and a current-to-voltage gainsetting.
 12. A multi-mode radio frequency (RF) transmitter comprises: abaseband processing module, when in a first mode, is coupled to convertfirst outbound signals into first symbols that include first phaseinformation and amplitude information and, when in a second mode, iscoupled to convert second outbound signals into second symbols thatinclude second phase information, and wherein the baseband processingmodule generates power level information when in the second mode;up-conversion module coupled to convert the first phase information ofthe first symbols into first phase modulated RF signals when thebaseband processing module is in the first mode and coupled to convertthe second phase information of the second symbols into second phasemodulated RF signals when the baseband processing module is in thesecond mode; a digital to analog conversion module including: a digitalto analog converter coupled to convert the amplitude information of thedata symbols into analog amplitude adjust signals when the basebandprocessing module and coupled to the power level information into analogpower level signals; a sample and hold circuit coupled to sample theanalog power level signals to produce a sampled analog power levelsignals; and a switch module coupled to provide the analog amplitudeadjust signals as an output of the DAC module when the basebandprocessing module is in the first mode and to output the analog powerlevel signals to the sample and hold circuit when the basebandprocessing module is in a second mode, wherein the sampled analog powerlevel signals provides the output of the DAC module in the second mode;and a power amplifier module coupled to amplify the first phasemodulated RF signals in accordance with the analog amplitude adjustsignals to produce first outbound RF signals when the basebandprocessing module is in the first mode and coupled to amplify the secondphase modulated RF signals in accordance with the sampled analog powerlevel signals to produce second outbound RF signals when the basebandprocessing module is in the second mode.
 13. The multi-mode RFtransmitter of claim 12, wherein the digital to analog convertercomprises: a sigma-delta modulator coupled to convert to the amplitudeinformation or the power level information into a sigma-delta modulatedsignal; a current amplifier section coupled to convert the sigma-deltamodulated signal into an analog current; and a voltage to current modulecoupled to convert the analog current into the analog amplitude adjustsignals or the analog power level signals.
 14. The multi-mode RFtransmitter of claim 13, wherein the voltage to current modulecomprises: a variable current source coupled to produce a referencecurrent based on the analog current; and an impedance coupled to producethe analog amplitude adjust signals or the analog power level signalsbased on the reference current.
 15. The multi-mode RF transmitter ofclaim 13, wherein the impedance comprises: a variable impedance coupledto produce the analog signal in accordance with a current-to-voltagegain setting.
 16. The multi-mode RF transmitter of claim 13, wherein thevoltage to current module comprises: the variable current source coupledto produce a reference current based on the analog current and acurrent-to-voltage gain setting.